#ifndef _NVIDIA_ACL_DATATYPE_H_
#define _NVIDIA_ACL_DATATYPE_H_

//ACL
typedef enum {
    ACL_DT_UNDEFINED = -1,
    ACL_FLOAT = 0,
    ACL_FLOAT16 = 1,
    ACL_INT8 = 2,
    ACL_INT32 = 3,
    ACL_UINT8 = 4,
    ACL_INT16 = 6,
    ACL_UINT16 = 7,
    ACL_UINT32 = 8,
    ACL_INT64 = 9,
    ACL_UINT64 = 10,
    ACL_DOUBLE = 11,
    ACL_BOOL = 12,
    ACL_STRING = 13,
} nvidia_aclDataType;

typedef enum {
    ACL_FORMAT_UNDEFINED = -1,
    ACL_FORMAT_NCHW = 0,
    ACL_FORMAT_NHWC = 1,
    ACL_FORMAT_ND = 2,
    ACL_FORMAT_NC1HWC0 = 3,
    ACL_FORMAT_FRACTAL_Z = 4,
    ACL_FORMAT_NC1HWC0_C04 = 12,
    ACL_FORMAT_FRACTAL_NZ = 29,
} nvidia_aclFormat;

typedef enum {
    ACL_DEBUG = 0,
    ACL_INFO = 1,
    ACL_WARNING = 2,
    ACL_ERROR = 3,
} nvidia_aclLogLevel;


//DVPP
// Supported Pixel Format
typedef enum nvidia_acldvppPixelFormat {
    PIXEL_FORMAT_YUV_400 = 0, // 0
    PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 1, // 1
    PIXEL_FORMAT_YVU_SEMIPLANAR_420 = 2, // 2
    PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 3, // 3
    PIXEL_FORMAT_YVU_SEMIPLANAR_422 = 4, // 4
    PIXEL_FORMAT_YUV_SEMIPLANAR_444 = 5, // 5
    PIXEL_FORMAT_YVU_SEMIPLANAR_444 = 6, // 6
    PIXEL_FORMAT_YUYV_PACKED_422 = 7, // 7
    PIXEL_FORMAT_UYVY_PACKED_422 = 8, // 8
    PIXEL_FORMAT_YVYU_PACKED_422 = 9, // 9
    PIXEL_FORMAT_VYUY_PACKED_422 = 10, // 10
    PIXEL_FORMAT_YUV_PACKED_444 = 11, // 11
    PIXEL_FORMAT_RGB_888 = 12, // 12
    PIXEL_FORMAT_BGR_888 = 13, // 13
    PIXEL_FORMAT_ARGB_8888 = 14, // 14
    PIXEL_FORMAT_ABGR_8888 = 15, // 15
    PIXEL_FORMAT_RGBA_8888 = 16, // 16
    PIXEL_FORMAT_BGRA_8888 = 17, // 17
    PIXEL_FORMAT_YUV_SEMI_PLANNER_420_10BIT = 18, // 18
    PIXEL_FORMAT_YVU_SEMI_PLANNER_420_10BIT = 19, // 19
    PIXEL_FORMAT_YVU_PLANAR_420 = 20, // 20
    PIXEL_FORMAT_YVU_PLANAR_422,
    PIXEL_FORMAT_YVU_PLANAR_444,
    PIXEL_FORMAT_RGB_444 = 23,
    PIXEL_FORMAT_BGR_444,
    PIXEL_FORMAT_ARGB_4444,
    PIXEL_FORMAT_ABGR_4444,
    PIXEL_FORMAT_RGBA_4444,
    PIXEL_FORMAT_BGRA_4444,
    PIXEL_FORMAT_RGB_555,
    PIXEL_FORMAT_BGR_555,
    PIXEL_FORMAT_RGB_565,
    PIXEL_FORMAT_BGR_565,
    PIXEL_FORMAT_ARGB_1555,
    PIXEL_FORMAT_ABGR_1555,
    PIXEL_FORMAT_RGBA_1555,
    PIXEL_FORMAT_BGRA_1555,
    PIXEL_FORMAT_ARGB_8565,
    PIXEL_FORMAT_ABGR_8565,
    PIXEL_FORMAT_RGBA_8565,
    PIXEL_FORMAT_BGRA_8565,
    PIXEL_FORMAT_RGB_BAYER_8BPP = 50,
    PIXEL_FORMAT_RGB_BAYER_10BPP,
    PIXEL_FORMAT_RGB_BAYER_12BPP,
    PIXEL_FORMAT_RGB_BAYER_14BPP,
    PIXEL_FORMAT_RGB_BAYER_16BPP,
    PIXEL_FORMAT_BGR_888_PLANAR = 70,
    PIXEL_FORMAT_HSV_888_PACKAGE,
    PIXEL_FORMAT_HSV_888_PLANAR,
    PIXEL_FORMAT_LAB_888_PACKAGE,
    PIXEL_FORMAT_LAB_888_PLANAR,
    PIXEL_FORMAT_S8C1,
    PIXEL_FORMAT_S8C2_PACKAGE,
    PIXEL_FORMAT_S8C2_PLANAR,
    PIXEL_FORMAT_S16C1,
    PIXEL_FORMAT_U8C1,
    PIXEL_FORMAT_U16C1,
    PIXEL_FORMAT_S32C1,
    PIXEL_FORMAT_U32C1,
    PIXEL_FORMAT_U64C1,
    PIXEL_FORMAT_S64C1,
    PIXEL_FORMAT_YUV_SEMIPLANAR_440 = 1000,
    PIXEL_FORMAT_YVU_SEMIPLANAR_440,
    PIXEL_FORMAT_FLOAT32,
    PIXEL_FORMAT_BUTT,
    PIXEL_FORMAT_UNKNOWN = 10000
} acldvppPixelFormat;

// Stream Format
typedef enum nvidia_acldvppStreamFormat {
    H265_MAIN_LEVEL = 0,
    H264_BASELINE_LEVEL,
    H264_MAIN_LEVEL,
    H264_HIGH_LEVEL
} acldvppStreamFormat;

// Supported Channel Mode
enum nvidia_acldvppChannelMode {
    DVPP_CHNMODE_VPC = 1,
    DVPP_CHNMODE_JPEGD = 2,
    DVPP_CHNMODE_JPEGE = 4
};

// Supported Border Type
enum nvidia_acldvppBorderType {
    BORDER_CONSTANT = 0,
    BORDER_REPLICATE,
    BORDER_REFLECT,
    BORDER_REFLECT_101
};

// Venc parameter type
enum nvidia_aclvencChannelDescParamType {
    ACL_VENC_THREAD_ID_UINT64 = 0,
    ACL_VENC_CALLBACK_PTR,
    ACL_VENC_PIXEL_FORMAT_UINT32,
    ACL_VENC_ENCODE_TYPE_UINT32,
    ACL_VENC_PIC_WIDTH_UINT32,
    ACL_VENC_PIC_HEIGHT_UINT32,
    ACL_VENC_KEY_FRAME_INTERVAL_UINT32,
    ACL_VENC_BUF_ADDR_PTR,
    ACL_VENC_BUF_SIZE_UINT32,
    ACL_VENC_RC_MODE_UINT32,
    ACL_VENC_SRC_RATE_UINT32,
    ACL_VENC_MAX_BITRATE_UINT32,
    ACL_VENC_MAX_IP_PROP_UINT32
};


#endif


